The present invention relates to the field of semiconductor chip packaging.
In the construction of semiconductor chip assemblies, it has been found desirable to interpose encapsulating material between and/or around elements of the semiconductor assemblies in an effort to reduce and/or redistribute the strain and strain on the connections between the semiconductor chip and a supporting circuitized substrate during operation of the chip, and to seal the elements against corrosion.
Ball grid array (xe2x80x9cBGAxe2x80x9d) packaged and chip scale packaged (xe2x80x9cCSPxe2x80x9d) semiconductor chips and flip chip attachment solutions are connected to external circuitry through contacts on a surface of the chip. To save area on a supporting substrate, such as a printed wiring board (xe2x80x9cPWBxe2x80x9d), these chips are directly connected/soldered to the substrates and from there connected to external circuitry on other parts of the substrate. The chip contacts are either disposed in regular grid array patterns, substantially covering the face surface of the chip (commonly referred to as an xe2x80x9carea arrayxe2x80x9d) or in elongated rows extending parallel to and adjacent each edge of the chip front surface. Many of the techniques for attachment run into problems because of the thermal expansion mismatch between the material the chip is composed of and the material the supporting circuitized substrate is made of, such as a PWB. In other words, when the chip is in operation, the chip heats up and also heats its supporting substrate thereby causing both the chip and the substrate to expand. When the heat is removed, the chip and substrate both contract. This heating and cooling process is referred to as xe2x80x9cthermal cycling.xe2x80x9d Since the heat is being generated in the chip, the chip will heat up more quickly and will typically get hotter than its supporting substrate. The materials comprising both the chip and the substrate have inherent expansion and contraction rates, referred to as their coefficients of thermal expansion (xe2x80x9cCTExe2x80x9d), which causes them to expand and contract at different rates and in different degrees when subjected to the same thermal conditions. This thermal expansion mismatch between the chips and the substrate places considerable mechanical stress and strain on the connections between the chip contacts and corresponding bond pads on the substrate.
BGA and CSP technology refers to a large range of semiconductor packages which use interconnection processes such as wirebonding, beam lead, tape automated bonding (xe2x80x9cTABxe2x80x9d) or the like as an intermediate connection step to interconnect the chip contacts to the exposed package terminals. This results in a device which can be tested prior to mechanical attachment to the bond pads on supporting substrate. The BGA or CSP packaged chips are then typically interconnected with their supporting substrates using standard tin-lead solder connections. In most such packaged devices, the mechanical stress/strain due to thermal cycling is almost completely placed on the solder connections between the chip and the substrate. However, solder was never intended to undergo such forces and commonly undergoes significant elastic solder deformation causing the solder to crack due to fatigue brought on by the thermal cycling. When the solder connections have smaller diameters, thermal cycling has an even more profound fatiguing affect on the solder. This has driven efforts in the packaging art to modify the solder and other elements of the packages so that they may better withstand the thermal cycling forces.
As the features of semiconductor chip packages continue to be reduced in size, as in the case of CSPs, the number of chips packed into a given area will be greater and thus the heat dissipated by the each of these chips will have a greater effect on the thermal mismatch problem. Further, the solder cracking problem is exacerbated when more than one semiconductor chip is mounted in a package, such as in a multi-chip module. As more chips are packaged together, more heat will be dissipated by each package which, in turn, means the interconnections between a package and its supporting substrate will encounter greater mechanical stress due to thermal cycling. Further, as more chips are integrated into multi-chip modules, each package requires additional interconnections thereby increasing the overall rigidity of the connection between the module and its supporting substrate.
Certain designs have reduced solder connection fatigue by redistributing the thermal cycling stress into a portion of the chip package itself. An example of such a design is shown in U.S. Pat. Nos. 5,148,265 and 5,148,266, the disclosure of which is incorporated herein by reference. One disclosed embodiment of these patents shows the use of a chip carrier in combination with a compliant layer to reduce the CTE mismatch problems. Typically, the compliant layer includes an elastomeric layer which, in the finished package, is disposed between the chip carrier and the face surface of the chip. The compliant layer provides resiliency to the individual terminals, allowing each terminal to move in relation to its electrically connected chip contact to accommodate CTE mismatch as necessary during testing, final assembly and thermal cycling of the device.
In some arrangements used heretofore, the compliant layer was formed by stenciling a thermoset resin onto the chip carrier and then curing the resin. Next, additional resin was applied to the exposed surface of the cured layer, this additional resin was partially cured, and the resulting tacky adhesive surface was used to bond the elastomeric layer to the chip and chip carrier. Once attached, the entire structure was heated and fully cured. Although this process is effective, further improvement would be desirable. The ambient gas can be occasionally entrapped when the chip carrier and die are affixed to the compliant layer. The entrapped gas can create voids and gas bubbles in the encapsulation of the surface of the die by the encapsulation material. These voids/bubbles allow moisture and other contamination to come into direct contact with the surface of the die. Accordingly, care must be taken to prevent such entrapment. This adds to the expense of the process.
In the flip-chip mounting technique, the contact bearing face surface of the chip opposes a bond pad bearing supporting substrate. Each contact on the device is joined by a solder connection to a corresponding bond pad on the supporting substrate, as by positioning solder balls on the substrate or device, juxtaposing the device with the substrate in the front-face-down orientation and momentarily reflowing the solder. The flip-chip technique yields a compact assembly, which occupies an area of the substrate no larger than the area of the chip itself. However, flip-chip assemblies suffer from significant problems when encountering thermal cycling stress because the sole thermal cycling stress-bearing elements are the solder connections, as described above in relation to the BGA and CSP packages. In the case of flip chip devices, there is no package to redistribute the thermal cycling stress. Because of this, significant work has been done in the art to make the flip chip solder connections more reliable. However, to keep the chip""s standoff from the substrate to a minimum, the solder connections have a typical diameter of between about five and eight thousandths of an inch (xe2x80x9cmilsxe2x80x9d), too small to provide much real mechanical compliance. In an attempt to solve this problem, a curable liquid underfill is flowed between the chip and its attached substrate, enclosing the solder connections. The underfill is then cured into a rigid form which has a CTE that is closely matched to the solder material. The aim of the underfill is to reduce the stress caused by CTE mismatch by redistributing the stress more uniformly over the entire surface of the chip, supporting substrate and solder balls. Examples of the use of underfill materials may be found in U.S. Pat. Nos. 5,120,678, 5,194,930, 5,203,076 and 5,249,101. All of these prior art solutions are aimed at reducing the shear stress endured by the interconnections caused by thermal cycling. However, each of these solutions also encounters significant problems such as insufficient compliancy, voids and process cost. Most significant among these costs is reducing the voiding problem which occurs when the underfill flows between the chip and the substrate and traps gas therebetween. If this gas is not removed, it will typically quickly expand during a heating cycle of the chip. The force associated with the expanding gas can cause the solder connections to crack or otherwise become unreliable. Yet, presently, the underfill process involves a very costly and time-consuming process of allowing the underfill to flow very slowly between the chip and the substrate to try to avoid voids. After the underfill has flowed completely between the chip and the substrate, the assembly will then be subjected to one or more vacuuming steps in a further attempt to remove any voids in the underfill material.
Despite these and other efforts in the art, still further improvements in interconnection technology would be desirable.
The present invention provides a method of eliminating voids and gas bubbles within the encapsulation used in attaching and packaging microelectronic devices which solves the aforementioned problems in the art. The present invention further provides an effective method of filling cavities and channels during encapsulation of a plurality of semiconductor chips formed on a semiconductor wafer.
In one embodiment, the method includes providing a substantially void and bubble free underfill for a semiconductor wafer having a plurality of flip chip assemblies. Typically, a flip chip device is electrically and mechanically attached to a circuitized substrate, such as a PWB, by a plurality of conductive members, which are most typically a plurality of solder balls. These solder balls provide an electrical path from each chip contact to a respective bond pad on the substrate. The solder balls further provide a gap or standoff between the wafer and hence each flip chip device and its substrate. This gap is then sealed on all sides of the flip chip device with a curable liquid encapsulant so that either a void (vacuum) or an area containing a first gas is thereby created. An isostatic or hydrostatic pressure is then applied to the semiconductor wafer assembly causing the encapsulant to flow into the gap and around the solder balls. An energy is applied to cure the encapsulant once the void/bubble has been completely removed thereby ensuring that new voids and/or bubbles do not re-occur between the flip chip device and the substrate. Typically, heat and/or ultra-violet radiation are used as the applied energy.
In another embodiment of the present invention, the method includes creating a substantially void/bubble free interposer layer between a semiconductor wafer having a plurality of microelectronic components and a sheet-like substrate. According to this method, an interposer layer is injected into a gap between each of the microelectronic components and the substrate such that any voids or gas bubbles are sealed within the gap. Isostatic or hydrostatic pressure is then applied to the entire semiconductor wafer assembly which causes the total volume for the voids/bubbles to be reduced to the point where they are substantially eliminated from the interposer layer. A further step of applying energy, such as heat, is employed to cure the interposer layer thereby ensuring that future void/bubble do not occur.
The injecting step may include providing a curable, liquid encapsulant at each edge of the gap between the microelectronic components and the substrate prior to the step of applying pressure, effectively sealing the space between the component and the substrate. When the pressure is then applied, it causes the sealed volume to be reduced thereby allowing the encapsulant to flow into the gap and form a substantially void/bubble free interposer layer.
A still further embodiment of the present invention includes a method of treating an interposer layer for a semiconductor wafer assembly to provide a substantially void/bubble free interposer layer. An interposer layer is first disposed between a semiconductor wafer having a plurality of semiconductor chips and a sheet-like substrate such that any voids within or at the boundaries of the interposer are sealed within the assembly. An isostatic or hydrostatic pressure is then applied to the assembly thereby reducing the volume of the voids/bubbles and substantially eliminating them from the interposer layer.
The foregoing and other objects and advantages of the present invention will be better understood from the following Detailed Description of a Preferred Embodiment, taken together with the attached figures.